Patent · US Active

Via array design for multi-layer redistribution circuit structure

US11776899B2 · kind B2 · utility

0Cited by

0References

19Claims

0Family size

Assignee

MEDIATEK INC. · TW

Inventors

Che-Hung Kuo · Hsinchu, TW
Hsing-Chih Liu · Baoshan, TW

Key dates

Filing date	Feb 18, 2021
Grant date	Oct 3, 2023
Priority date	—
Expiry date	Oct 24, 2041

Classification

Technology area (CPC H)Electricity
CPC primaryH05K2201/0979
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

An interconnect structure for a redistribution layer includes an intermediate via land pad; a cluster of upper conductive vias abutting the intermediate via land pad and electrically coupling the intermediate via land pad to an upper via land pad; and an array of lower conductive vias electrically coupling the intermediate via land pad with a lower circuit pad. The array of lower conductive vias is arranged within a horseshoe-shaped via array region extending along a perimeter of the intermediate via land pad. The array of lower conductive vias arranged within the horseshoe-shaped via array region does not overlap with the cluster of upper conductive vias.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.