Closed loop lane synchronization for optical modulation
US11777702B2 · kind B2 · utility
1Cited by
19References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 11, 2021 |
| Grant date | Oct 3, 2023 |
| Priority date | — |
| Expiry date | May 11, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B10/50
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A system for transmitting signals via serial links includes a plurality of lanes for combining data onto a transmission media, a skew detector configured to detect skew among two of the plurality of lanes, and a variable delay circuit controlled by the skew detector, configured to delay the start of a clock signal to circuitry of one of the plurality of lanes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.