Three-dimensional memory device with punch-through-resistant word lines and methods for forming the same
US11778818B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 2020 |
| Grant date | Oct 3, 2023 |
| Priority date | — |
| Expiry date | Mar 2, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An alternating stack of insulating layers and electrically conductive layers, a retro-stepped dielectric material portion overlying stepped surfaces of the alternating stack, and memory stack structures extending through the alternating stack are formed over a substrate. A patterned etch mask layer including discrete openings is formed thereabove. Via cavities through an upper region of the retro-stepped dielectric material portion by performing a first anisotropic etch process. Metal plates are selectively formed on physically exposed surfaces of a first subset of the electrically conductive layers by a selective metal deposition process. A subset of the via cavities without any metal plates therein are vertically extended downward by performing a second anisotropic etch process while the metal plates protect underlying electrically conductive layers. Via cavities can be formed without punching through electrically conductive layers. Contact via structures can be formed in the via cavities by depositing at least one conductive material therein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.