Reconfigurable neural network processing based on subgraph recognition
US11782706B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2021 |
| Grant date | Oct 10, 2023 |
| Priority date | — |
| Expiry date | Dec 17, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one example, a method comprises: receiving input codes, wherein the input codes represent a computational dataflow graph; traversing the computational dataflow graph to identify single-entry-single-exit (SESE) subgraphs of the computational dataflow graph, wherein each SESE subgraph has a sequence of nodes comprising a root node and a child node and representing a sequence of element-wise operators, wherein the root node receives a single input tensor, and wherein the child node outputs a single output tensor; determining a merged operator for each SESE subgraph; and generating executable instructions for the computational dataflow graph to be executed by a hardware accelerator having a first execution unit and a second execution unit, wherein the executable instructions comprise first executable instructions for the merged operators targeted at the first execution unit, and second executable instructions for other operators of the computational dataflow graph targeted at the second execution unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.