PCIe interface and interface system
US11782792B2 · kind B2 · utility
2Cited by
13References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2021 |
| Grant date | Oct 10, 2023 |
| Priority date | — |
| Expiry date | Jun 17, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device is provided to include: a transceiver configured to transmit and receive data; and a skip ordered set (SKP OS) control logic in communication with the transceiver and configured to generate an SKP OS and control the transceiver to transmit the SKP OS and a data block to a link connecting to an external device and including a plurality of lanes. The SKP OS control logic is configured to increase or decrease transmission interval of the SKP OS based on a transmission history of the SKP OS, in response to an entry of the link to a recovery state that is used to recover the link from an error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.