Refresh operation in multi-die memory
US11783882B2 · kind B2 · utility
1Cited by
4References
16Claims
0Family size
Inventors
Key dates
| Filing date | Jul 19, 2021 |
| Grant date | Oct 10, 2023 |
| Priority date | — |
| Expiry date | Jul 19, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, apparatuses, and systems for staggering refresh operations to memory arrays in different dies of a three-dimensional stacked (3DS) memory device are described. A 3DS memory device may include one die or layer of that controls or regulates commands, including refresh commands, to other dies or layers of the memory device. For example, one die of the 3DS memory may delay a refresh command when issuing the multiple concurrent memory refreshes would cause some problematic performance condition, such as high peak current, within the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.