Inventor · Boise, ID, US

Matthew A. Prather

75Patents
5h-index
29Co-inventors
68Inventor score

Filing activity: Aug 12, 2013 → May 1, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US10817371B2 Error correction in row hammer mitigation and target row refresh Physics 14 Active
US9921980B2 Apparatuses and methods for configuring I/Os of memory for hybrid memory modules Physics 6 Active
US10395721B1 Memory devices configured to provide external regulated voltages Emerging Cross-Sectional Technologies 6 Active
US10489316B1 Methods for performing multiple memory operations in response to a single command and memory devices and systems employing the same Physics 5 Active
US11074126B2 Methods for error count reporting with scaled error count information, and memory devices employing the same Physics 5 Active
US11538508B2 Memory module multiple port buffer techniques Physics 4 Active
US10424356B2 Methods for on-die memory termination and memory devices and systems employing the same Physics 4 Active
US10657081B2 Individually addressing memory devices disconnected from a data bus Physics 4 Active
US11294762B2 Error correction in row hammer mitigation and target row refresh Physics 4 Active
US11221913B2 Error check and scrub for semiconductor memory device Physics 3 Active
US10846248B2 Methods for performing multiple memory operations in response to a single command and memory devices and systems employing the same Physics 2 Active
US11069394B2 Refresh operation in multi-die memory Physics 2 Active
US10282134B2 Methods of synchronizing memory operations and memory systems employing the same Physics 2 Active
US11886754B2 Apparatuses and methods for configuring I/Os of memory for hybrid memory modules Physics 2 Active
US10282133B2 Memory devices with programmable latencies and methods for operating the same Physics 2 Active
US10754801B2 Individually addressing memory devices disconnected from a data bus Physics 2 Active
US10423363B2 Apparatuses and methods for configuring I/OS of memory for hybrid memory modules Physics 2 Active
US10552087B2 Methods for performing multiple memory operations in response to a single command and memory devices and systems employing the same Physics 2 Active
US11687410B2 Error check and scrub for semiconductor memory device Physics 2 Active
US11379158B2 Apparatuses and methods for configuring I/Os of memory for hybrid memory modules Physics 1 Active
US11783882B2 Refresh operation in multi-die memory Physics 1 Active
US11436169B2 Individually addressing memory devices disconnected from a data bus Physics 1 Active
US10983934B2 Individually addressing memory devices disconnected from a data bus Physics 1 Active
US11545199B2 Methods for on-die memory termination and memory devices and systems employing the same Physics 1 Active
US10810145B2 Methods for performing multiple memory operations in response to a single command and memory devices and systems employing the same Physics 1 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.