Method for coloring circuit layout and system for performing the same
US11790145B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2022 |
| Grant date | Oct 17, 2023 |
| Priority date | — |
| Expiry date | Jun 29, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/70466
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.