Tiling a primitive in a graphics processing system by edge-specific testing of a subset of tiles in a rendering space
US11790480B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 28, 2022 |
| Grant date | Oct 17, 2023 |
| Priority date | — |
| Expiry date | Jan 28, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2210/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In tile-based graphics processing systems, a tiling unit determines which tiles of a rendering space a primitive is in, such that the primitives in a tile can be rendered. Rather than performing tiling calculations for each tile in a bounding box for a primitive, tiling tests can be performed for a subset of the tiles. Then the results of the tiling tests for the subset of tiles can be used to determine whether the primitive is in other tiles which are located within a region bounded by two or more of the tiles of the subset. In this way the tiling process can be implemented without performing tiling calculations for all of the tiles in the bounding box for a primitive. Reducing the number of tiling calculations can help to improve the efficiency of the graphics processing system (in terms of speed and power consumption) for rendering a primitive.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.