Pattern fidelity enhancement
US11791161B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2020 |
| Grant date | Oct 17, 2023 |
| Priority date | — |
| Expiry date | Aug 2, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/306
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a method for semiconductor manufacturing in accordance with some embodiments. The method includes providing a substrate and a patterning layer over the substrate and forming a plurality of openings in the patterning layer. The substrate includes a plurality of features to receive a treatment process. The openings partially overlap with the features from a top view while a portion of the features remains covered by the patterning layer. Each of the openings is free of concave corners. The method further includes performing an opening expanding process to enlarge each of the openings and performing a treatment process to the features through the openings. After the opening expanding process, the openings fully overlap with the features from the top view.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.