Integrated circuit structures including backside vias
US11791331B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2021 |
| Grant date | Oct 17, 2023 |
| Priority date | — |
| Expiry date | Nov 18, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/16225
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed herein are integrated circuit (IC) structures including backside vias, as well as related methods and devices. In some embodiments, an IC structure may include: a device layer, wherein the device layer includes a plurality of active devices; a first metallization layer over the device layer, wherein the first metallization layer includes a first conductive pathway in conductive contact with at least one of the active devices in the device layer; a second metallization layer under the device layer, wherein the second metallization layer includes a second conductive pathway; and a conductive via in the device layer, wherein the conductive via is in conductive contact with at least one of the active devices in the device layer and also in conductive contact with the second conductive pathway.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.