Single gated 3D nanowire inverter for high density thick gate SOC applications
US11791380B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2019 |
| Grant date | Oct 17, 2023 |
| Priority date | — |
| Expiry date | Feb 14, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0186
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a substrate, and a first transistor of a first conductivity type over the substrate. In an embodiment, the first transistor comprises a first semiconductor channel, and a first gate electrode around the first semiconductor channel. In an embodiment, the semiconductor device further comprises a second transistor of a second conductivity type above the first transistor. The second transistor comprises a second semiconductor channel, and a second gate electrode around the second semiconductor channel. In an embodiment, the second gate electrode and the first gate electrode comprise different materials.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.