Delay circuit and clock error correction device including the same
US11791811B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2022 |
| Grant date | Oct 17, 2023 |
| Priority date | — |
| Expiry date | Jun 14, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00241
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay circuit for a clock signal includes a first signal generator, a first inverting circuit, a second signal generator and a second inverting circuit. The first signal generator is configured to generate a plurality of first switching signals based on a delay code. The first inverting circuit includes a plurality of first inverters that are selectively turned on in response to the plurality of first switching signals, respectively, and is configured to adjust a first delay time for both of a first edge and a second edge of the clock signal. The second signal generator is configured to generate a plurality of second switching signals based on a duty code. The second inverting circuit includes a plurality of second pull-up units and a plurality of second pull-down units, respective ones of the plurality of second pull-up units or respective ones of the plurality of second pull-down units are selectively turned on in response to respective ones of the plurality of second switching signals. The second inverting circuit is configured to adjust a second delay time for the first edge, the second edge, or both of the first edge and the second edge of the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.