Semiconductor structure and manufacturing method thereof
US11792974B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2021 |
| Grant date | Oct 17, 2023 |
| Priority date | — |
| Expiry date | Jun 21, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/315
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate including a peripheral region, wherein the peripheral region includes a wire lead-out area, and the substrate is arranged with a plurality of discrete bit line structures; a dielectric layer formed between the adjacent bit line structures, wherein the peripheral region is arranged with a first contact hole; a wire lead-out area with a second through hole; a filling layer filling part of a first contact hole, wherein a remaining part of the first contact hole is defined as a first through hole; a first conductive layer located in the first through hole and the second through hole; and a conductive connecting wire located over the dielectric layer and being in contact with the first conductive layer in the wire lead-out area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.