Word line structure of three-dimensional memory device
US11792989B2 · kind B2 · utility
0Cited by
18References
18Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 25, 2021 |
| Grant date | Oct 17, 2023 |
| Priority date | — |
| Expiry date | Oct 25, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53257
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device comprises a substrate, a stack structure on the substrate, and at least one gate line slit extending along a first direction substantially parallel to a top surface of the substrate, and dividing the stack structure into at least two portions. The stack structure includes at least one connection portion that divides the at least one gate line slit, and conductively connects the at least two portions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.