Three-dimensional memory device including a string selection line gate electrode having a silicide layer
US11792994B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 2022 |
| Grant date | Oct 17, 2023 |
| Priority date | — |
| Expiry date | Apr 20, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/663
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional memory device is provided. The three-dimensional memory device may include a substrate, a cell stack, a string selection line gate electrode, a lower vertical channel structure, an upper vertical channel structure, and a bit line. The string selection line gate electrode may include a lower string selection line gate electrode and an upper string selection line gate electrode formed on an upper surface of the lower string selection line gate electrode. The lower string selection line gate electrode may include N-doped poly-crystalline silicon. The upper string selection line gate electrode may include silicide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.