Method of manufacturing semiconductor devices
US11796922B2 · kind B2 · utility
1Cited by
12References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2019 |
| Grant date | Oct 24, 2023 |
| Priority date | — |
| Expiry date | May 19, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31138
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.