Hardware-software collaborative address mapping scheme for efficient processing-in-memory systems
US11797201B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2022 |
| Grant date | Oct 24, 2023 |
| Priority date | — |
| Expiry date | May 16, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Approaches are provided for implementing hardware-software collaborative address mapping schemes that enable mapping data elements which are accessed together in the same row of one bank or over the same rows of different banks to achieve higher performance by reducing row conflicts. Using an intra-bank frame striping policy (IBFS), corresponding subsets of data elements are interleaved into a single row of a bank. Using an intra-channel frame striping policy (ICFS), corresponding subsets of data elements are interleaved into a single channel row of a channel. A memory controller utilizes ICFS and/or IBFS to efficiently store and access data elements in memory, such as processing-in-memory (PIM) enabled memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.