Competitive machine learning accuracy on neuromorphic arrays with non-ideal non-volatile memory devices
US11797833B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2017 |
| Grant date | Oct 24, 2023 |
| Priority date | — |
| Expiry date | Jun 16, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Optimized synapses for neuromorphic arrays are provided. In various embodiments, first and second single-transistor current sources are electrically coupled in series. The first single-transistor current source is electrically coupled to both a first control circuit and second control circuit, free of any intervening logic gate between the first single-transistor current source and either one of the control circuits. The second single-transistor current source is electrically coupled to both the first control circuit and the second control circuit, free of any intervening logic gate between the second single-transistor current source and either one of the control circuits. A capacitor is electrically coupled to the first and second single-transistor current sources. A read circuit is electrically coupled to the capacitor. The first and second single-transistor current sources are adapted to charge the capacitor only when concurrently receiving a control signal from both the first and second control circuits. The first and second single-transistor current sources are adapted to discharge the capacitor only when concurrently receiving a control signal from both the first and second c…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.