Transfer latch tiers
US11798631B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 2021 |
| Grant date | Oct 24, 2023 |
| Priority date | — |
| Expiry date | Oct 24, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Read and write circuitry, described herein, comprises data latches, each data latch connected to a bit line and arranged in a same column as the bit line; and transfer latches, each transfer latch connected to a data latch and arranged in a same column as the data latch. Further, circuitry described herein is configured to: transfer a word to and from the transfer latches of a first column and the subset of transfer latches of a second column; transfer a first portion of the word between the transfer latches of the first column and data latches of the first column that are connected to the transfer latches of the first column; and transfer a second portion of the word between the subset of transfer latches and data latches of the second column that are connected to the subset of transfer latches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.