Memory device and operation method thereof
US11798639B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 2021 |
| Grant date | Oct 24, 2023 |
| Priority date | — |
| Expiry date | Jun 22, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device and an operation method thereof are disclosed. The memory device includes a P-well region, a common source line, a ground selection line, at least one dummy ground selection line, a plurality of word lines, at least one dummy string selection line, a string selection line, at least one bit line and at least one memory string. The gates of a plurality of memory cells of the memory string are connected to the word lines. The operation method includes the following steps. Performing a read operation and applying a read voltage on the selected word line. Applying a pass voltage on other unselected word lines and the ground selection lines, etc. Before ending of the read operation, firstly decreasing voltages of the string selection line and the dummy string selection line in advance, then increasing voltage of the bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.