Hierarchical ROM encoder system for performing address fault detection in a memory system
US11798644B2 · kind B2 · utility
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22Claims
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Key dates
| Filing date | Feb 11, 2022 |
| Grant date | Oct 24, 2023 |
| Priority date | — |
| Expiry date | Apr 24, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various embodiments are disclosed for performing address fault detection in a memory system using a hierarchical ROM encoding system. In one embodiment, a hierarchical ROM encoding system comprises two levels of ROM encoders that are used to detect an address fault. In another embodiment, a hierarchical ROM encoding system comprises three levels of ROM encoders that are used to detect an address fault.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.