Manufacturing method of package device
US11798853B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 2021 |
| Grant date | Oct 24, 2023 |
| Priority date | — |
| Expiry date | Feb 5, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/829
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a manufacturing method of a package device, which includes providing a carrier substrate, a first conductive layer, and a release layer, where the carrier substrate has a device region and a peripheral region, and the first conductive layer and the release layer are disposed on the carrier substrate. The method further includes forming a second conductive layer on the release layer in the device region, where at least one of the first and second conductive layers includes a first pad in the peripheral region. The second conductive layer includes a second pad electrically connected to the first pad through the first conductive layer. The method also includes performing an inspection step to provide an input signal to one of the first and second pads, and to receive an output signal from another of the first and second pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.