Device package substrate structure and method therefor
US11798871B2 · kind B2 · utility
0Cited by
6References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2020 |
| Grant date | Oct 24, 2023 |
| Priority date | — |
| Expiry date | Jun 8, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/49816
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device substrate is provided. The substrate includes an embedded trace substrate (ETS) portion. The ETS portion includes a first conductive layer embedded in the ETS portion at a first major surface. A portion of the first conductive layer is patterned to form a signal line. A non-conductive layer is disposed between the first conductive layer and a second conductive layer second embedded in the ETS portion. A third conductive layer is formed over the first major surface of the ETS portion. The third conductive layer is configured to form a stripline with the signal line of the first conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.