Semiconductor epitaxial wafer
US11799011B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2022 |
| Grant date | Oct 24, 2023 |
| Priority date | — |
| Expiry date | Apr 15, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/824
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Provided is a semiconductor epitaxial wafer, including a substrate, a first epitaxial structure, a first ohmic contact layer and a second epitaxial stack structure. It is characterized in that the ohmic contact layer includes a compound with low nitrogen content, and the ohmic contact layer does not induce significant stress during the crystal growth process. Accordingly, the second epitaxial stack structure formed on the ohmic contact layer can have good epitaxial quality, thereby providing a high-quality semiconductor epitaxial wafer for fabricating a GaAs integrated circuit or a InP integrated circuit. At the same time, the ohmic contact properties of ohmic contact layers are not affected, and the reactants generated during each dry etching process are reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.