Semiconductor device structure with uniform threshold voltage distribution and method of forming the same
US11799017B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2022 |
| Grant date | Oct 24, 2023 |
| Priority date | — |
| Expiry date | Apr 13, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/151
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embodiment method includes: forming a semiconductor liner layer on exposed surfaces of a fin structure that extends above a dielectric isolation structure disposed over a substrate; forming a first capping layer to laterally surround a bottom portion of the semiconductor liner layer; forming a second capping layer over an upper portion of the semiconductor liner layer; and annealing the fin structure having the semiconductor liner layer, the first capping layer, and the second capping layer thereon, the annealing driving a dopant from the semiconductor liner layer into the fin structure, wherein a dopant concentration profile in a bottom portion of the fin structure is different from a dopant concentration profile in an upper portion of the fin structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.