Wafer level passive heat spreader interposer to enable improved thermal solution for stacked dies in multi-chips package and warpage control

US11804470B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Xavier Francois Brun · Hillsboro, US
• Kaizad Mistry · Lake Oswego, US
• Paul R. Start · Chandler, US
• Nisha Ananthakrishnan · Chandler, US
• Yawei Liang · Chandler, US
• Jigneshkumar P. Patel · Amherst, US
• Sairam Agraharam · Chandler, US
• Liwei Wang · Phoenix, US

Key dates

• Filing date: Aug 22, 2019
• Grant date: Oct 31, 2023
• Expiry date: Feb 28, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/3511
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a plurality of first dies on a substrate, an encapsulation layer over the first dies and the substrate, an interface layer over the first dies and the encapsulation layer, and a passive heat spreader on the interface layer, wherein the interface layer thermally couples the first dies to the passive heat spreader. The passive heat spreader includes a silicon (Si) or a silicon carbide (SiC). The interface layer includes a silicon nitride (SiN) material, a silicon monoxide (SiO) material, a silicon carbon nitride (SiCN) material, or a thermal adhesive material. The semiconductor package may include a plurality of second dies and the substrate on a package substrate, a thermal interface material (TIM) over the second dies, the passive heat spreader, and the package substrate, and a heat spreader over the TIM and the package substrate.