Transistor with center fed gate
US11804527B2 · kind B2 · utility
0Cited by
6References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2021 |
| Grant date | Oct 31, 2023 |
| Priority date | — |
| Expiry date | Feb 1, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/111
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A transistor includes a source contact connected to a Through-Silicon Via (TSV). A drain contact is connected to a first pad. A gate structure is interposed between the source contact and the drain contact. A second pad is connected to the gate structure, the second pad comprising a first side diametrically opposed to a second side, and a third side interposed therebetween, the source contact proximal to the third side, a first portion of the first side and a second portion of the second side.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.