Phase-locked loop with phase information multiplication
US11804846B2 · kind B2 · utility
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3References
20Claims
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Key dates
| Filing date | Nov 5, 2019 |
| Grant date | Oct 31, 2023 |
| Priority date | — |
| Expiry date | Nov 5, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase-locked loop (PLL) includes a phase-frequency detector that compares a reference signal to a feedback signal. The difference in phase between the reference signal and the feedback signal is encoded as digital pulses on one or more outputs of the phase-frequency detector. The digital output pulses from the phase-frequency detector are duplicated and delayed multiple times in a non-overlapping manner before being input to the loop filter or voltage controlled oscillator (VCO) of the PLL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.