System and method for data loss and data latency management in a network-on-chip with buffered switches
US11805080B2 · kind B2 · utility
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8Claims
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Key dates
| Filing date | Jul 16, 2022 |
| Grant date | Oct 31, 2023 |
| Priority date | — |
| Expiry date | Jul 16, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/9047
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A buffered switch system for end-to-end data congestion and traffic drop prevention. More specifically, and without limitation, the various aspects and embodiments of the invention relates to the management of buffered switch to prevent the balancing act of buffer sizing, latency, and traffic drop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.