Manufacturing method of memory device
US11805644B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2022 |
| Grant date | Oct 31, 2023 |
| Priority date | — |
| Expiry date | May 2, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
Provided is a manufacturing method of a memory device, including: forming a stacked layer on a substrate; patterning the stacked layer to form a plurality of openings in the stacked layer; forming a spacer on a sidewall of the openings; performing a first etching process by using the spacer as a mask to form a plurality of stack structures, wherein the spacer is embedded in the stack structures, such that a width of an upper portion of the stack structures is less than a width of a lower portion thereof; forming a dielectric layer on the stack structures and the spacer; and respectively forming a plurality of contact plugs on the substrate between the stack structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.