Memory and forming methods and control methods thereof
US11805701B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 11, 2020 |
| Grant date | Oct 31, 2023 |
| Priority date | — |
| Expiry date | Aug 15, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/80
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes: a substrate, having a plurality of active regions arranged in an array and a plurality of word lines extending in a first direction, the active regions being inclined at a preset angle to the word lines, the active region having at least one access transistor; a plurality of bit lines, extending in a second direction perpendicular to the first direction; magnetic tunnel junctions, one end of the magnetic tunnel junction is electrically connected to one of bit lines and another end of the magnetic tunnel junction is electrically connected to two access transistors, the two access transistors electrically connected to the magnetic tunnel junction being located in two adjacent active regions, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.