Contention tracking for processor cache management
US11809319B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 20, 2022 |
| Grant date | Nov 7, 2023 |
| Priority date | — |
| Expiry date | Jan 23, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/123
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The technology disclosed herein involves tracking contention and using the tracked contention to manage processor cache. The technology can be implemented in a processor's cache controlling logic and can enable the processor to track which locations in main memory are contentious. The technology can use the contentiousness of locations to determine where to store the data in cache and how to allocate and evict cache lines in the cache. In one example, the technology can store the data in a shared cache when the location is contentious and can bypass the shared cache and store the data in the private cache when the location is uncontentious. This may be advantageous because storing the data in shared cache can reduce or avoid having multiple copies in different private caches and can reduce the cache coherency overhead involved to keep copies in the private caches in sync.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.