Shailender Chaudhry
133Patents
22h-index
48Co-inventors
90Inventor score
Filing activity: May 17, 1999 → Jan 20, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7206903B1 | Method and apparatus for releasing memory locations during transactional execution | Physics | 114 | Expired |
| US7930695B2 | Method and apparatus for synchronizing threads on a processor that supports transactional memory | Physics | 72 | Active |
| US6721944B2 | Marking memory elements based upon usage of accessed information during speculative execution | Physics | 71 | Expired |
| US6862664B2 | Method and apparatus for avoiding locks by speculatively executing critical sections | Physics | 70 | Expired |
| US7398355B1 | Avoiding locks by transactionally executing critical sections | Physics | 67 | Expired |
| US7818510B2 | Selectively monitoring stores to support transactional program execution | Physics | 63 | Active |
| US7617421B2 | Method and apparatus for reporting failure conditions during transactional execution | Physics | 62 | Active |
| US6938130B2 | Method and apparatus for delaying interfering accesses from other threads during transactional program execution | Physics | 61 | Expired |
| US8327188B2 | Hardware transactional memory acceleration through multiple failure recovery | Physics | 59 | Active |
| US7461208B1 | Circuitry and method for accessing an associative cache with parallel determination of data and data availability | Physics | 58 | Expired |
| US7269694B2 | Selectively monitoring loads to support transactional program execution | Physics | 56 | Expired |
| US7421465B1 | Arithmetic early bypass | Physics | 53 | Active |
| US7089374B2 | Selectively unmarking load-marked cache lines during transactional program execution | Physics | 40 | Expired |
| US7389383B2 | Selectively unmarking load-marked cache lines during transactional program execution | Physics | 34 | Expired |
| US8984264B2 | Precise data return handling in speculative processors | Physics | 34 | Active |
| US7676636B2 | Method and apparatus for implementing virtual transactional memory using cache line marking | Physics | 31 | Active |
| US6684398B2 | Monitor entry and exit for a speculative thread during space and time dimensional execution | Physics | 28 | Expired |
| US6704862B1 | Method and apparatus for facilitating exception handling using a conditional trap instruction | Physics | 26 | Expired |
| US6247027A | Facilitating garbage collection during object versioning for space and time dimensional computing | Emerging Cross-Sectional Technologies | 26 | Expired |
| US7216202B1 | Method and apparatus for supporting one or more servers on a single semiconductor chip | Physics | 26 | Expired |
| US7509481B2 | Patchable and/or programmable pre-decode | Physics | 25 | Expired |
| US7917698B2 | Method and apparatus for tracking load-marks and store-marks on cache lines | Physics | 23 | Active |
| US6430649B1 | Method and apparatus for enforcing memory reference dependencies through a load store unit | Physics | 22 | Expired |
| US10642744B2 | Memory type which is cacheable yet inaccessible by speculative instructions | Physics | 21 | Active |
| US7571304B2 | Generation of multiple checkpoints in a processor that supports speculative execution | Physics | 21 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.