Data-buffer component with variable-width data ranks and configurable data-rank timing
US11809345B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2022 |
| Grant date | Nov 7, 2023 |
| Priority date | — |
| Expiry date | Feb 22, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4265
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.