Implementing fixed-point polynomials in hardware logic
US11809795B2 · kind B2 · utility
0Cited by
5References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 18, 2021 |
| Grant date | Nov 7, 2023 |
| Priority date | — |
| Expiry date | Oct 28, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method implements fixed-point polynomials in hardware logic. In an embodiment the method comprises distributing a defined error bound for the whole polynomial between operators in a data-flow graph for the polynomial and optimizing each operator to satisfy the part of the error bound allocated to that operator. The distribution of errors between operators is updated in an iterative process until a stop condition (such as a maximum number of iterations) is reached.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.