Systems and methods to store a tile register pair to memory

US11809869B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Raanan Sade · Migdal HaEmek, IL
• Simon Rubanovich · Haifa, IL
• Amit Gradstein · Binyamina - Givat Ada, IL
• Zeev Sperber · Jerusalem, IL
• Alexander Heinecke · San Jose, US
• Robert Valentine · Kiryat Tivon, IL
• Mark J. Charney · Lexington, US
• Bret L. Toll · Hillsboro, US
• Jesus Corbal · King City, US
• Elmoustapha Ould-Ahmed-Vall · Chandler, US
• Menachem Adelman · Haifa, IL

Key dates

• Filing date: Dec 29, 2017
• Grant date: Nov 7, 2023
• Expiry date: Dec 29, 2037

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F9/3877
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Embodiments detailed herein relate to systems and methods to store a tile register pair to memory. In one example, a processor includes: decode circuitry to decode a store matrix pair instruction having fields for an opcode and source and destination identifiers to identify source and destination matrices, respectively, each matrix having a PAIR parameter equal to TRUE; and execution circuitry to execute the decoded store matrix pair instruction to store every element of left and right tiles of the identified source matrix to corresponding element positions of left and right tiles of the identified destination matrix, respectively, wherein the executing stores a chunk of C elements of one row of the identified source matrix at a time.