Memory device including multiple memory chips and data signal lines and a method of operating the memory device
US11810638B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2021 |
| Grant date | Nov 7, 2023 |
| Priority date | — |
| Expiry date | Jan 21, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06562
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An operating method of a memory device includes selecting a receiver from a plurality of receivers of each memory chip of a plurality of memory chips included in the memory device as a first receiver. The plurality of memory chips share a plurality of data signal lines, each memory chip includes a plurality of on-die termination (ODT) resistors, and the plurality of ODT resistors are respectively connected to the plurality of receivers of each memory chip. The method further includes setting each ODT resistor which is connected to a first receiver to a first resistance value, setting ODT resistors which are connected to receivers which are not first receivers to a second resistance value, and setting an amplification strength of an equalizer circuit of each first receiver by performing training operations. Each data signal line of the plurality of data signal lines is respectively connected to a first receiver.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.