Semiconductor devices with stacked silicide regions
US11810826B2 · kind B2 · utility
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13References
20Claims
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Key dates
| Filing date | May 27, 2022 |
| Grant date | Nov 7, 2023 |
| Priority date | — |
| Expiry date | May 27, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0193
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device with multiple silicide regions is provided. In embodiments a first silicide precursor and a second silicide precursor are deposited on a source/drain region. A first silicide with a first phase is formed, and the second silicide precursor is insoluble within the first phase of the first silicide. The first phase of the first silicide is modified to a second phase of the first silicide, and the second silicide precursor being soluble within the second phase of the first silicide. A second silicide is formed with the second silicide precursor and the second phase of the first silicide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.