FinFET device with different liners for PFET and NFET and method of fabricating thereof
US11810827B2 · kind B2 · utility
0Cited by
50References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2021 |
| Grant date | Nov 7, 2023 |
| Priority date | — |
| Expiry date | Oct 21, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/859
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a P-type Field Effect Transistor (PFET) and an NFET. The PFET includes an N-well disposed in a substrate, a first fin structure disposed over the N-well, a first liner layer disposed over the N-well, and a second liner layer disposed over the first liner layer. The first liner layer and the second liner layer include different materials. The NFET includes a P-well disposed in the substrate, a second fin structure disposed over the P-well, a third liner layer disposed over the P-well. The third liner layer and the second liner layer include the same materials.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.