Heterogeneous integration of radio frequency transistor chiplets having interconnection tuning circuits
US11810876B1 · kind B1 · utility
1Cited by
10References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2023 |
| Grant date | Nov 7, 2023 |
| Priority date | — |
| Expiry date | Mar 10, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/6683
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An electronic assembly has a host wafer having a first circuit including passive devices for the purpose of one of tuning or matching networks. Chiplets are placed in the cavities. At least one chiplet has a second circuit including at least one transistor or switch device and passive tuning circuits including at least one of a stabilization network, a gain boosting network, a power delivery network, or a low-noise network. Electrical interconnects between the chiplets and wafer electrically connect the first circuitry to the second circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.