Method for integrating surface-electrode ion trap and silicon photoelectronic device, integrated structure, and three-dimensional structure
US11810986B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2020 |
| Grant date | Nov 7, 2023 |
| Priority date | — |
| Expiry date | Dec 31, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/103
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method for integrating a surface-electrode ion trap and a silicon optoelectronic device, and an integrated structure. A silicon structure and a grating are formed on a wafer. A first dielectric layer, a second dielectric layer, a third dielectric layer, and a fourth dielectric layer are sequentially deposited above the wafer. An epitaxy opening is provided in the first dielectric layer to form single-photon avalanche detectors. First contacts vias connecting the detectors, and through silicon vias reaching a back surface of the wafer, are provided in the second dielectric layer and the third dielectric layer, respectively. Electrodes, the second contact vias and the third contact vias are provided in the fourth dielectric layer. The first contact vias are connected to a first electrode via the second contact vias, and the through silicon vias are connected to the first electrode and a second electrode via the third contact vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.