Latch circuit, memory device and method
US11811404B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 12, 2021 |
| Grant date | Nov 7, 2023 |
| Priority date | — |
| Expiry date | Nov 12, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A latch circuit includes a latch clock generator configured to generate a latched clock signal based on a clock signal and a first enable signal, and an input latch coupled to the latch clock generator to receive the latched clock signal. The input latch is configured to generate a latched output signal based on the latched clock signal and an input signal. In response to the first enable signal having a disabling logic level, the latch clock generator is configured to set a logic level of the latched clock signal to a corresponding disabling logic level, regardless of the clock signal. The latch clock generator includes a first inverter configured to generate an inverted signal of the first enable signal, and a NAND gate coupled to the first inverter to receive the inverted signal of the first enable signal. The NAND gate is configured to generate the latched clock signal based on the clock signal and the inverted signal of the first enable signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.