Method and system for semiconductor wafer defect review
US11816411B2 · kind B2 · utility
2Cited by
3References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 24, 2020 |
| Grant date | Nov 14, 2023 |
| Priority date | — |
| Expiry date | Nov 30, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2207/30148
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor wafer defect detection system captures test images of a semiconductor wafer. The system analyzes the test images with an analysis model trained with a machine learning process. The analysis model generates simulated integrated circuit layouts based on the test images. The system detects defects in the semiconductor wafer by comparing the simulated integrated circuit layouts to reference integrated circuit layouts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.