Logic cell structures and related methods
US11816412B2 · kind B2 · utility
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12References
20Claims
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Key dates
| Filing date | Apr 16, 2021 |
| Grant date | Nov 14, 2023 |
| Priority date | — |
| Expiry date | Nov 19, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of forming an integrated circuit structure is provided. The method includes: providing a logic cell structure including a first input node, a second input node, and a pulling network connected to a reference voltage and an output node, wherein the pulling network includes a plurality of transistor segments; determining a delay associated with at least one of the first input node and the second input node; and connecting the plurality of transistor segments to the first input node, the second input node and the output node based at least in part on the determined delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.