Systems, methods, and apparatuses for matrix operations
US11816483B2 · kind B2 · utility
8Cited by
48References
21Claims
0Family size
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Key dates
| Filing date | Dec 29, 2017 |
| Grant date | Nov 14, 2023 |
| Priority date | — |
| Expiry date | Dec 29, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30109
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments detailed herein relate to matrix (tile) operations. For example, decode circuitry to decode an instruction having fields for an opcode and a memory address, and execution circuitry to execute the decoded instruction to store configuration information about usage of storage for two-dimensional data structures at the memory address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.