Method of enabling sparse neural networks on memresistive accelerators
US11816563B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 2019 |
| Grant date | Nov 14, 2023 |
| Priority date | — |
| Expiry date | Mar 26, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/0495
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of storing a sparse weight matrix for a trained artificial neural network in a circuit including a series of clusters. The method includes partitioning the sparse weight matrix into at least one first sub-block and at least one second sub-block. The first sub-block includes only zero-value weights and the second sub-block includes non-zero value weights. The method also includes assigning the non-zero value weights in the at least one second sub-block to at least one cluster of the series of clusters of the circuit. The circuit is configured to perform matrix-vector-multiplication (MVM) between the non-zero value weights of the at least one second sub-block and an input vector during an inference process utilizing the artificial neural network. The sub-blocks containing all zero elements are power gated, thereby reducing overall energy consumption for inference.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.