Programming multi-level memory cells
US11817145B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2022 |
| Grant date | Nov 14, 2023 |
| Priority date | — |
| Expiry date | Mar 10, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for programming multi-level memory cells are described. After a first pass, an offset in the form of one or more offset pulses, may be applied to MLCs that are in a state of a higher level. The offset may be applied before or during a first part of a second pass. The offset may move the signals of the cells before the cells are finally programmed so as to avoid potential overlaps between the unprogrammed cells and cells that are programmed to the lower half of the final levels during the second pass. The offset cells may then be further moved to the other levels in the higher half of the final levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.