Conductive route patterning for electronic substrates

US11817349B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Jeremy Ecton · Gilbert, US
• Brandon C. Marin · Chandler, US
• Leonel Arana · Phoenix, US
• Matthew Tingey · Hillsboro, US
• Oscar Ojeda · Chandler, US
• Hsin-Wei Wang · Chandler, US
• Suddhasattwa Nad · Chandler, US
• Srinivas V. Pietambaram · Gilbert, US
• Gang Duan · Beijing, CN

Key dates

• Filing date: Mar 5, 2020
• Grant date: Nov 14, 2023
• Expiry date: Mar 15, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/32134
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A conductive route for an integrated circuit assembly may be formed using a sequence of etching and passivation steps through layers of conductive material, wherein the resulting structure may include a first route portion having a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, an etch stop structure on the first route portion, a second route portion on the etch stop layer, wherein the second route portion has a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, and a passivating layer abutting the at least one side surface of the second route portion.