BGA STIM package architecture for high performance systems
US11817364B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2018 |
| Grant date | Nov 14, 2023 |
| Priority date | — |
| Expiry date | Aug 8, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/16235
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments include semiconductor packages and methods of forming such packages. A semiconductor package includes a die on a package substrate, an integrated heat spreader (IHS) on the package substrate and above the die, and a solder thermal interface material (STIM) coupling the die to the IHS. The semiconductor package includes a low-temperature solder (LTS) paste comprising an alloy of tin and bismuth (Bi), and the LTS paste on a bottom surface of the package substrate having a ball grid array. The LTS paste may have a weight percentage of Bi greater than 35% and a melting point less than or equal to a melting point of the STIM, where the STIM includes indium. The weight percentage of Bi may be between approximately 35% to 58%. The semiconductor package may include a solder ball coupling the LTS paste on the package substrate to the LTS paste on a second package substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.